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Espressif Systems /ESP32-H2 /PCR /I2S_RX_CLKM_CONF

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Interpret as I2S_RX_CLKM_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0I2S_RX_CLKM_DIV_NUM 0I2S_RX_CLKM_SEL 0 (I2S_RX_CLKM_EN)I2S_RX_CLKM_EN 0 (I2S_MCLK_SEL)I2S_MCLK_SEL

Description

I2S_RX_CLKM configuration register

Fields

I2S_RX_CLKM_DIV_NUM

Integral I2S clock divider value
I2S_RX_CLKM_SEL

Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
I2S_RX_CLKM_EN

Set 1 to enable i2s_rx function clock
I2S_MCLK_SEL

This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data